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| DDR-SDRAM T ermination Regulator BD3530F Au Description BD3530F is a regulator developed as termination power supply of standard DDR-SDRAM that is used for PC. Industry's highest speed of transient response characteristic is realized. The built-in FET can sink and source load current of 3A(max.) Waveform quality when data is transferred at high speed can't be deteriorated. BD3530F meets the bus line standards SSTL-2 of DDR-SDRAM. High-reliability can be realized for any applications using DDR-SDRAM. Au Dimension (Unit : mm) 5.00.2 8 5 6.20.3 4.40.2 1 4 0.150.1 0.1 1.50.1 0.11 1.27 0.40.1 SOP8 Au Features 1) 2) 3) 4) 5) 6) Built-in push-pull regulator for termination(VTT) Built-in reference voltage circuit(VREF) Built-in enable function Built-in under voltage lock out circuit Package SOP8 Built-in thermal shut down circuit Au Applications Note personal computer, Desktop personal computer Absolute Maximum RatingsAi Ta=25CAj Parameter Input voltage Termination input voltage VDDQ reference voltage Power dissipation 1 Power dissipation 2 Operating temperature range Storage temperature range Symbol VCC VTT_IN VDDQ Pd1 Pd 2 Topr Tstg -10 Limits 7 7 7 560 690 A An 1 An 1 An 1 An 2 An 3 Unit V V V mW mW +100 -55 A +150 C C An Should not exceed Pd. 1 An Reduced by 4.48mW for each increase in Ta of 1C over 25C(With no heat sink). 2 An Reduced by 5.52mW for each increase in Ta of 1C over 25C(PCB(70mmA~ 3 70mmA~ 1.6mm)glass epoxy mounting.) 0.3Min. Au Recommended Operating ConditionsAi Ta=25CAj Parameter Input voltage Termination input voltage Symbol VCC VTT_IN Min. 4.5 1.7 Typ. Max. 5.5 2.6 Unit V V *This product is designed for protection against radioactive rays. Au Electrical characteristics (Unless otherwise noted, Ta=25C, VCC=5V, VEN=3V, VDDQ=2.5V, VTT_IN=2.5VAj Parameter Standby current Bias current An Design Guarantee Symbol IST ICC VTT ITT+ ITTHRON LRON VREF IREF+ IREFVUVLO E VUVLO Min. VREF-30mV 3 1/2A~ VDDQ-50mV Typ. 2 VREF 0.15 0.15 1/2A~ VDDQ Max. 10 4 VREF+30mV -3 0.3 0.3 1/2A~ VDDQ+50mV Unit A mA V A A V mA mA V mV VEN=0V Conditions Io=-3A to 3A, Ta=0Ae to 100Ae An IREF=-10mA to 10mA Ta=0Ae to 100Ae An 10 4.2 100 20 -20 4.35 160 -10 4.5 220 VCC : Sweep up VCC : Sweep down Au Application Circuit VCC VDDQ VTT_IN VCC VDDQ 25k UVLO VCC VCC VTT_IN VCC Thermal Protection TSD + Enable Reference Block - EN 25k TSD EN UVLO Liner N-MOS Driver VTT VTT TSD EN UVLO VTTS VREF 1/2A~ VDDQ BD3530F GND |
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